(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit manufacturing and more particularly to methods and structures for protecting integrated circuits from electrostatic discharge.
(2) Description of Prior Art
Electrostatic discharge (ESD) is a phenomenon that occurs during handling of semiconductor integrated circuit devices, which may lead to destructive effects on such devices. Various circuits have been disclosed that provide protection from ESD. Li et al. In U.S. Pat. No. 5,477,414 and U.S. Pat. No. 5,689,133 propose an ESD protection circuit that combines a split bipolar transistor with a transistor layout, which exhibits tolerance to ESD events. A method of fabricating low voltage zener-triggered silicon controlled rectifier for ESD protection in integrated circuits is disclosed in U.S. Pat. No. 5,856,214 to Yu. A method for fabricating an ESD protection device is disclosed in U.S. Pat. No. 6,051,457 to Ito, in which the ESD protection device can be incorporated in an integrated circuit with a passive component or with an active component. U.S. Pat. No. 6,057,184 to Brown et al. and U.S. Pat. No. 6,169,301 to Ishikawa et al. are related patents.
Cascaded diode structures, also called diode strings, are commonly used non-breakdown ESD protection devices. Typical applications are for Vdd to Vss clamps, coupling clamps Vdd to Vdd0, Vss to Vss0 and high voltage tolerant I/O. These are shown in FIGS. 1-3, where for purposes of illustration the number of diodes in the cascaded diode structures, 2, is taken to be 4. The single diode, 4, in FIG. 2 represents the n junction on the p-substrate. Region 6 of FIG. 3 is an I/O pad and the diode 8 represents an ESD protection device.
The cascaded diode structure is shown in FIG. 4, where p, 10, and n, 12, regions are implanted in n-wells, 14, formed in a p-substrate, 16, and, except for the in and out regions, n and p regions of successive n-wells are electrically connected. Because the n-wells form rectifying junctions with the p-substrate, the cascaded diode made in this way actually forms a chain of Darlington coupled PNP transistors, as shown in FIG. 5. Referring to FIG. 6, there is presented the relationship of the transistor currents at any stage, k, of the cascaded diode structure in terms of the PNP bipolar current gain, b. The current into the k transistor is Ik, the current into the substrate from the k transistor is (b/1+b)Ik and the current into the (k+1) transistor is ({fraction (1/1)}+b)Ik=Ik+1. If there are m transistors, then the current out of the cascaded diode structure, Iout, not passing into the substrate, is related to the current into the cascaded diode structure, Iin by Iout=Iin(1+b)m. The current into the substrate from all the transistors, Iss, is the difference, Iinxe2x88x92Iout and thus Iss=Iin(1xe2x88x92({fraction (1/1)}+b)m. It is seen that when b is large almost all the current passes into the substrate. For example, for b=1 and m=4, {fraction (15/16)} of the current passes into the substrate. Since potential differences exist across cascaded diode structures during normal operation, and not just under EDS events, such large substrate leakage currents can pose serious problems. Maloney, in U.S. Pat. No. 5,530,612, proposes techniques to alleviate this problem by utilizing circuitry in addition to cascaded diode structures. This invention shows that modifying the cascaded diode structure can substantially diminish the substrate leakage current, without introducing other circuit elements.
It is a primary objective of the invention to provide modifications in the structure of the cascaded diode that results in substantial reduction of substrate leakage current. Such reduction is accomplished by significantly reducing the PNP bipolar current gain by means of a deep n-well under the n-well of the usual cascaded diode structure. The gain is reduced to much less than unity when the PNP base width is doubled by the added deep n-well and the base concentration is increased. Consequently the substrate leakage current is greatly reduced.
A cascaded diode acting as an EDS protection device with reduced substrate leakage current is disclosed. The cascaded diode is composed of a chain of coupled similar elemental diodes, each composed of an n-well in a p-substrate, the n-well having p regions and n regions, and a deep n-well disposed under and connected to the n-well. The first elemental diode has its p region electrically connected to a pin or pad that is the higher potential end of a portion of an integrated circuit to be protected, its n region electrically connected to the p region of an intermediate elemental diode. The p region of an intermediate diode is connected electrically to the n region of the preceding elemental diode and the n region of an intermediate elemental diode is connected electrically to the p region of the following elemental diode. A last elemental diode has its p region electrically connected to the n region of the preceding elemental diode and its n region electrically connected to a pad or pin that is the end of the portion of an integrated circuit.